Chapter 10. Redesign

Figure 10.1. MC14500 CPU board

MC14500 CPU board

The redesign moved all the not 15V CMOS logic into the FPGA. The analog timers using potentiometers got replaced by hex switches controlling digital timers in the FPGA. The original design used two 8bit EPROM access cycles to get a command for the MC14500 and its IO-address. The FPGA implementation used a 16bit wide memory to get it with a single access. The big debug connector got not implemented, since the FPGA allows to implementing an internal logic analyzer that is obviously much more powerful.

Figure 10.2. Replacement CPU board

Replacement CPU board


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