MC14500 CPU board

The implementation uses synchronous logic and avoids dependencies on asynchronous delays. Therefore all is based on the clock. The MC14500 latches the 4 instruction bits on the falling clock edge. The rising clock is used by the MC14500 to read and write the IO's. So the program counter can update the ROM on the rising clock edge. The IO-address from the ROM changes also on the rising clock edge and a IO-address is required to select the IO to be read or written. To have a synchronous design and not run into timing issues the IO-address from the ROM is latched on the falling edge into D-Flip-Flops. So the IO-address applied to the IO's does not change while the MC14500 reads or writes the IO's.

To reduces the number of chips, the program counter is free running and can not be reseted by the MC14500. This gives a constant cycle time for the program. Constant cycle times are common on SPS. The cycle time is small enough so a human being will not notice a reaction delay.

The timing regarding the data output is not well specified in the MC14500 datasheet. To prevent an eventually bus fight that could damage the MC14500 a 1k resistor is added between MC14500 and the input chip. If a bus fight would occur then the current will be limited.

The design allows too be in-circuit programmed and controlled by a daughter board. Again there could be some collision between outputs so all potential dangerous signals are feed via 1k resistors to the connector.

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