Hardware issues

Something not very well documented is a possible bus contention (fight) on the bidirectional data line of the MC14500 or its attached peripherals during the change of the write signal. Bus contention occurs when more than one chip drives the data line at the same time with probably a different signal level. It can be safely assumed that the MC14500 chip designers had the timing inside the chip under control. So it is just an chip external issue. Different solution exist or are possible:

  1. Some designs simply ignore it

  2. A serial resistor could be added to limit the current to the specified level in case a bus fight occurs

  3. Some designs use a OR-gate feed by X1 and Write and use then the output for the OE~ of the peripheral chips. This might be a good solution, especially if the OR-gate adds some delay.

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