Chapter 9. FPGA implementation

The FPGA implementation of the MC14500 CPU used a Altera Cyclone III FPGA and the Quartus II development environment. Unfortunately both the Cyclone III FPGA and Quartus II are now outdated. Cyclone III are no more supported by newest Altera development environment.

Features of the MC14500 CPU are:

  1. Cyclone FPGA EP3C5E144C8 in the rather small QFP 144 case

  2. 16 inputs plus 16 outputs that can be read back

  3. 16 bit wide ROM (2kByte) containing the program

  4. High speed

  5. All important signals available on the pins

  6. Embarrassing how little of the chips internal logic is used, leaving space for much more

  7. 1 bit wide RAM to store temporary data

  8. All CPU signals are fed to pins of the FPGA

Figure 9.1. FPGA implementation

FPGA implementation

Figure 9.2. Simulation of a program

Simulation of a program

Figure 9.3. The FPGA hardware

The FPGA hardware

The program running in the real hardware can be analyzed with the FPGA embedded logic analyzer.

Figure 9.4. FPGA Logic analyzer

FPGA Logic analyzer

Linurs Servernest startpage