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Chapter 4. Interface |  |
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Chapter 4. Interface | |
JTAG (Joint Test Action Group) is a standard interface to complexer chips that has been introduced to test assembled PCB's in the production. It has many functions as to read out the chip model, read and write pins and program the chips. Chips on a board can be connected in series, so the board needs just one JTAG interface, the TAP (Test Access Port) for the complete board.
The BSDL (Boundery Scan Definition language) file format (*.bsd) describes the JTAG interface for a device and uses a subset of VHDL.
BSDL files can be found at the manufacturers Website or others as https://bsdl.info/index.htm,
BSDL files support more than one case and therefore pinout. Download the file, open it and check the details
To have a BSDL file is vital in a open source and open world. The JTAG standard gives a lot of freedoms in length of the register and command codes. The BSDL file also holds the chips pin out and obviously knows the number of bits.
The SVF file format (*.svf) contains a number of high level commands to drive the JTAG bus. It is used by altera and xilinx to program chips. A SVF player reads a SVF file and does what is written in the file. This way the SVF player does not have to know anything about the attached device internals and can be dumb.
The Hardware uses 4 mandatory pins
Table 4.1. JTAG signals
| Signal | Direction at the Adapter | Description |
| TCK | Output | Test Clock |
| TDI | Output | Test Data Input (Data to Device) |
| TDO | Input | Test Data Output (Data from Device) |
| TMS | Output | Test Mode Select |
The pinout is unfortunately not standardized among the manufacturers even a 10pin male header on the board is quite common. Is the power supply 5V or 3V3 and who supplies who has to be clarified. There are also some optional signals in the 10 pin header.
Table 4.2. JTAG Adapter Incompatibilities
| Lattice/Vantis | Altera/Intel | AVR | |
| 1 | TCK (Out) | TCK (Out) | TCK |
| 2 | Gnd | Gnd | Gnd |
| 3 | TMS (Out) | TDO (In) | TDO |
| 4 | Gnd | Vcc | VTref (In) |
| 5 | TDI (Out) | TMS (Out) | TMS |
| 6 | Vcc (Target to Adapter) | (Out) | nSRST (In/Out Reset line) |
| 7 | TDO (In) | (In) | Vsupply (In, if the adapter required power) |
| 8 | Gnd | (Out) | nTRST (Out) |
| 9 | TRST (Out or Vcc) | TDI (Out) | TDI |
| 10 | Enable (Out or Gnd) | Gnd | Gnd |
A JTAG adapter is an universal device that moves data in to and out of a chip. JTAG adapters for Altera CPLD's can therefore also be used for programming Avr microprocessors.
A JTAG adapter can be used to
Program a device
debug a micro controller
Board testing for solder joints
Read signals back for analysis and troubleshooting
Replace single purpose Hardware
Obviously there are some performance issues when using a historic parallel printer port dongle. Today a ft232h USB JTAG adapter is a good option to have a universal state of the art open source DIY adapter.
https://github.com/shuckc/urjtag/blob/master/urjtag/doc/UrJTAG.txt or https://sourceforge.net/projects/urjtag/ is a tool for JTAG interfaces. It come with python bindings and installs the two command line programs jtag. See man jtag or jtag -h
jtag is interactive where commands as help cable will show the supported jtag adapters.
jtag -q suppresses the initial text when started
quit exits
Many adapters are rather old and use the parallel port of a PC.
For those old approach make sure the PC has a parallel port and the ppdev kernel driver is loaded and a /dev/parport0 file is created.
Adapters as Altera ByteBlaster require options, so type cable ByteBlaster help
To initialize, plug in the ByteBlaster and type cable ByteBlaster parallel 0x378 or cable ByteBlaster ppdev /dev/parport0 no error should be reported (when the ByteBlaster is plugged in)
cable UsbBlaster for a Altera USB Blaster or compatible as Terasic Blaster. Also here some additional parameters could be passed as cable UsbBlaster help shows but the default might be fine.
Attach the JTAG capable chip and run detect and a Atmel AVR might return
IR length: 4 Chain length: 1 Device Id: 00001001010100001000000000111111 (0x0950803F) Manufacturer: Atmel (0x03F) Unknown part! (1001010100001000) (/usr/share/urjtag/atmel/PARTS)
Knowing the Device ID it looks for available information in /usr/share/urjtag
If it appears as "Unknown part!" a directory containing the BSDL files can be passed bsdl path <path to directory holding bsdl files> or bsdl path . when they are in the current directory.
bsdl test checks if the BSDL files are free of errors. There is also the bsdl2jtag program that convers the bsdl files to UrJTAG internal format, since UrJTAG understands BSDL directly now, this program is obsolete, However it can be used to check if the BSDL files are free of errors.
The chip has to be identified correctly otherwise not much can be done. Even reading the Device Id could not work since size of the instruction register and code to select the Device ID could be different than expected.
detect will show then the file found to match the device as:
IR length: 4 Chain length: 1 Device Id: 00001001010100001000000000111111 (0x0950803F) Filename: ./ATMEGA324P.bsdl
print signals will show the device
print chain shows the status
include <path and file> allows to run commands located in a file. Repeating commands as setting the adapter cable and loading BSDL files can be put in such files.
There is also the ~/.jtag/rc file that gets read when jtag starts. To prevent this jtag -n or jtag --norc
jtag <file> allows to execute commands in a file and exits
detect reads the ID Code and does a lot more.
The same can be done with individual steps
reset brings it to a known state
print instructions shows the active and all other instructions
instruction IDCODE selects the ID Code Data register
shift ir is immediately required to shift the instruction register through the chain (and unloads the shift register to the instruction holding register). Observe the result with print chain
shift dr will shift the data register through the JTAG chain now load the data registers
dr out will read the selected data register in the device (ID Code) and outputs it
Once JTAG works and the chip is detected programming a device can be done using the svf player of UrJtag.
svf <filename>.svf stop progress
stop stops on error
progress shows the progress
There is one single Instruction Register (IR) and a couple of Data Registers (DR).
The TAP controller is a state machine that controls the behavior. It uses the TMS signal and the TCK clock (TMS is sampled on the rising edge of TCK) to select the the operation states. The optional TRST signal or 5 or more TCK with TMS=1 will bring back the state machine into the initial "test logic reset" state.
The "shift IR" state allows to clock in data from TDI to the instruction shift register (TMS is kept 0 during this). When passing the "update IR" state, the shift register will be loaded into the instruction hold register to be come effective.
Instructions set the registers to be put into the TDI and TDO chain:
Bypass Register is used to clock TDI into TDO (with on TCK delayed, since the DR is 1 bit long)
Device ID Register allows to read an identifier to define the used chip. Set IR to IDCODE (0b00001) and read 32 data bits back.
Boundary Scan Register (BSR), every pin has it bit. It allows to read from and write data to the pins, but it allows also connecting as an instrument to the pins to see the applications behavior,
The Data Registers can be written and read having TMS=0 and using TCK, TDI and TDO. Similar as the IR the shift register can be loaded into a holding register passing the "update DR" state. Also the other way is possible the load the shift register with data from the device (read or data output)
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